In 18-447, we will use this tool to verify that your Verilog code is, indeed, synthesizable.
I haven't tried myself, but there are two strategies to optimize a design.Įach output in my_module is optimized individually. Automatic synthesis script generation for synopsys design compiler Download PDF Info Publication number US6836877B1. Synopsys Design Compiler is a software package that compiles synthesizable Verilog into a netlist to target an ASIC standard cell library. Is there a set of DC commands that can achieve this? The best thing to do is to try a few sets of options and to continue with the best resulting one. I have experienced that sometimes ungrouping a whole project gives worse results (timing, area etc.). A synthesis tool takes an RTL hardware description and a standard cell library as input and produces a gate-level netlist as output. Different options and optimization strategies don't give the same results in all cases. RTL-to-Gates Synthesis using Synopsys Design Compiler 6.375 Tutorial 4 MaIn this tutorial you will gain experience using Synopsys Design Compiler (DC) to perform hardware synthesis. WHAT NEXT Make sure that you want the named port to exist in the given design, even though it has no nets connected. If it optimizes the design as a whole, is there an advantage to The Synopsys tools leave unconnected ports alone, with one exception that is, you specified that a given input port is opposite or equal to another input port in a design.
DC also has an option for the optimization strategy, I'll show below.
dont_touch) and synthesis options (ungrouping, boundary optimization etc.) permit. Design Compiler tries to optimize both of them as long as the constraints (e.g. There is no difference between an RTL design and a post-synthesis netlist. Use this command : cp –r lab03_ic_compiler /tmp/yourfoldernameĤ: Start the Synopsys IC Compiler graphical user interface (GUI) from your work directory, /tmp/yourfoldername.Does ungrouping different designs optimize mostly around theīoundaries or will optimize the whole design regardless of whetherĮach smaller module has been synthesized before or not? Tar –zxvf snps_design_flow_ Do not do this in the SDRIVE!!!!ĭ) Go to the unzipped folder “snps_design_flow_tutorial”Į) Copy the directory “lab03_ic_compiler” to your /tmp/yourfoldername directory using the command:
Make a work directory for this lab under /tmp folder called “yourfoldername” Do not do this lab on the SDRIVE!!!!, Do this under the directory /tmp/yourfoldernameĪ) download “snps_design_flow_” from to your SDRIVE using your web browser on the Windows machine.ī) copy this file to the directory “/tmp/yourfoldername “Ĭ) On the Linux machine, untar the file using the command